1. Field of the Invention
The invention relates to a reference current generating circuit, and particularly to a reference current generating circuit capable of compensating a deviation of a reference current from a preset value before shipment in advance.
2. Description of the Background Art
A sense circuit for a flash memory determines read data to be “1” when a cell current is larger than a reference current, and determines the read data to be “0” when a cell current is smaller than a reference current. Here, a memory cell is called “on-cell” if “1” is stored in the memory cell, and is called “off-cell” if “0” is stored in the memory cell.
A memory cell array in which such memory cells are arranged in a matrix has on-cell and off-cell currents which are distributed within certain ranges due to variation in characteristic of each memory cell. Consequently, the value of the reference current to be compared with the memory cell current is desirably set in an intermediate area between the lower limit of the on-cell current distribution and the upper limit of the off-cell current distribution.
Japanese Patent Application Publication No. 2005-302197, for example, discloses a method of reducing the effects of manufacturing process variation without adversely affecting reading speed in the following manner. A reference signal is supplied from a sense amplifier reference circuit to multiple sense amplifiers, and the gate sizes of respective P-channel MOS transistors formed in the sense amplifiers and the sense amplifier reference circuit are suitably designed.
However, a conventional reference current generating circuit has a problem in that a read operation margin is reduced because the reference current varies due to manufacturing process variation, operating temperature, and a power supply voltage. It is thus difficult to design a circuit which allows such variation.